Joseph Michael M. Mathana and Parthasarathy Rangarajan
SISO, ML-MAP, LLR, APP, reconfigurable
This paper presents a reconfigurable architecture for high perfor- mance turbo decoder based on Max-Log Maximum a Posteriori (ML-MAP) algorithm using sliding window technique. The pro- posed architecture with branch metric standardization and state metric reallocation techniques improve the speed performance of the soft input soft output (SISO) decoder and is also configured to sup- port three different constraint lengths. The intended reconfigurable decoder architecture has been implemented using Verilog HDL at RTL level and synthesized to investigate its performance in terms of area usage, timing delay and power. The power consumption of the device is measured using Synopsis Design Compiler – Simplicity Pre- mier with DCP 2008 tool. This architecture provides a throughput of 107 Mbit/s with a power consumption of about 66.6 mW.
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