Davide Marano, Giovanni Bonanno, Sergio Billotta, Massimiliano Belluso, Alessandro Grillo, Salvatore Garozzo, Giuseppe Romeo, Osvaldo Catalano, Giovanni La Rosa, Giuseppe Sottile, and Domenico Impiombato
Analogue circuits, front-end model, PSPICE simulations, silicon photomultipliers
The present paper is intended to implement and simulate the Extended Analogue Silicon-photomultiplier Integrated Read-Out Chip (EASIROC) fully analogue front-end model, in order to investigate its foremost characteristics and demonstrate its practical effectiveness when its analogue inputs are driven by the silicon photomultiplier (SiPM) signals. The circuit models of all functional blocks are described. Frequency and dynamic features of all circuit front-end sections are briefly addressed, and design mathematical equations are derived as well. PSPICE simulations of each single model are carried out to analyse and confirm its analogue behaviour.
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