M. Li, X. Wu, X. Zhu, and H. Wang (PRC)
GA, Reconfigurable Architecture, System Level Synthesis
As shown in recent experience, partially and dynamically reconfigurable architecture (DPRA) has been proved to be an efficient choice to improve function density, time to market, and flexibility. In order to deliver the greatest potential, delicate system level synthesis algorithm is needed. In this paper, a hierarchically constructed synthesis algorithm is presented, which can automatically choose the cheapest yet adequate reconfigurable device from the library, and optimally map TGs onto the chosen device. Unlike previous work, the proposed approach is based on realistic model that is extracted from Xilinx Virtex series. The model has full height vertical slices and pre partitioned fixed blocks. During synthesis, genetic algorithm is applied to both blocks partitioning and priority assignment, and initial strings are delicately constructed to promote the global efficiency.
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