T. Satou, K. Ootsu, A. Tsukikawa, T. Yokota, and T. Baba (Japan)
variable analysis, binary translation, multithreading, parallelizing.
Currently, we are now developing a binary transla tion system that translates single thread binary codes into multithreaded one. In order to generate efficient multithreaded codes, it is important to remove the unnecessary restrictions caused by dependencies be tween threads. However, register indirect memory ac cesses make it difficult to identify the target address of the memory access and, the dependencies between memory accesses. Without identifying them, we can not generate efficient multithreaded codes at binary code level. In order to understand the register and memory accesses of binary codes, this paper proposes the binary-level variable analysis method. We ap ply our proposed variable analysis method to an ac tual numerical application code, to generate the multi threaded code using the result of the analysis. And we evaluate the effectiveness of our method by executing the generated multithreaded binary code on a cycle based execution-driven multithread processor simula tor.
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