K. Gururaj, N. Guinde, R. Garg, M. Deoghare, A. Deshmukh, U. Dharmavaram, D. Chandok, N. Chakravarthy, R. Erukulla, S. Devireaddy, S. Papavassiliou, and D. Misra (USA)
Wireless Ad-Hoc Networks, VLSI design, Position guided Sliding window Protocol (PSR).
Mobile hosts and wireless networking hardware are becoming more widely available unlike before. The Position-guided Sliding window Routing protocol (PSR) [1] has been proposed for Ad-Hoc networks, and is based on the superposition of link-state and position-based routing algorithms. This is achieved by merging the processes of routing and mobility management by combining the use of geographic position with the adaptation of a hierarchical organization concept used for location database updating in Cellular Networks. This paper presents the architecture of the chip that can be used to implement the Position guided Sliding window Routing (PSR) protocol. The architecture of the chip is divided into three main blocks namely Updation or Transmitter, Data packet forwarding and Receiver block. All these blocks use a centralized Memory Unit to access the data and are linked to a Bus Arbitrator so as to handle the interrupts The Memory Unit has three Look Up Tables (LUT); Position LUT, Original LUT and Updation LUT. A VHDL model for this architecture was developed and simulated using the IEEE numeric_std package. This model was synthesized using Cadence Ambit BuildGates tool and the post synthesis simulations verified the functionality of the architecture.
Important Links:
Go Back
