Y.-C. Jiang and Y.-T. Lai (Taiwan)
Reconfigurable computing, system-on-chip, temporal partitioning, computer-aided design, design automation.
In reconfigurable computing systems, dynamically reconfigurable FPGA are evolving rapidly, due to their flexibility and high performance. The communication cost is one of important factors in dynamically reconfigurable FPGA. This paper proposes a scheduling technique based on network flow partitioning for the dynamically reconfigurable FPGA to reduce communication cost. We use a scheduling technique in which gate can not be replicated to minimize the communication cost. By constructing a graph the scheduling technique is converted to minimize communication cost. This algorithm was tested on a set of benchmark examples. The experimental results demonstrate effectiveness of this proposed algorithm.
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