A Novel Parallel Parity Checksum Generator Complying with ITU-T J.83 Annex B

E. Hong, E. Jung, D. Har, and J. Yim (Korea)

Keywords

J.83 Annex B, Parallel Parity Checksum

Abstract

This paper proposes a parallel architecture of a parity checksum generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conven tional serial processing architecture, leading to significant decrease in processing time for generating a parity check sum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

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• DOI:
• From Proceeding (573) Circuits, Signals, and Systems - 2007

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