B. Hong (USA)
Synchronization, Multi-core, Shared Variables, Lock
A new hardware-based design is presented to support shared accesses in multi-core processors. In the proposed design, instructions updating shared variables are issued by the processor cores but executed by the proposed hardware unit that is snooping on the bus. After issuing such an in struction, the processor core can proceed immediately with subsequent instructions. The proposed hardware unit as sumes the responsibility of buffering and sequentializing the multiple access requests from the processor cores. The proposed hardware is shown to be sequentially consistent for accesses to shared variables. Comparison against lock based synchronization shows that the proposed hardware design can significantly reduce synchronization overheads.
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