M.R.H. Fatemi, I. Jebril, and R. Salleh (Malaysia)
Cryptography, Elliptic curve, Bit-serial, Architecture
This paper describes an FPGA based hardware accelerator for elliptic curve cryptography. This accelerator performs binary polynomial basis operations in Galois Field GF ( ) using a microcoded structure. Microcode instructions support basic Galois Field operations regardless of encryption algorithms or keys. It uses a pipeline bit-serial architecture for the most computationally intensive Galois field operation (i.e., multiplication) with reduction. Due to its bit-serial architecture, it has regular structure, low power consumption, low cost area and a reduced number of pins which makes it suitable for hand held devices applications. For speeding up the design, we use the multi-word operand structure while it decreases the I/O pin requirements. In addition, a simple technique is used for immediate Galois field addition/subtraction operation to speed up the design further. The design is implemented in VHDL and the Xilinx ISE 8.2 and Modelsim XE are used for implementation and simulation, respectively. The clock frequency of design is around 180 MHz which can perform a scalar multiplication over GF ( ) in 1.1 µSec. m 2 m 2
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