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APPLICATION MAPPING OF MESH BASED-NOC USING MULTI-OBJECTIVE GENETIC ALGORITHM
R.K. Jena and G.K. Sharma
References
[1] E. Zitzler & L. Thiele, Multi-objective evolutionary algorithms:A comparative case study and the strength pareto approach,IEEE Transactions on Evolutionary Computation, 4 (3), 1999,257–271.
doi:10.1109/4235.797969
[2] J. Hu & R. Marculescu, Energy-aware mapping for tile-basedNoC architectures under performance constraints, in Asia &South Pacific Design Automation Conf., Yokohama, Japan,January 2003.
[3] J. Hu & R. Marculescu, Exploiting the routing flexibility forenergy/performance aware mapping of regular NoC architec-tures, in Proc. DATE ’03, Messe Munich, Germany, 2003,688–693.
[4] S. Murali & G.D. Micheli, Bandwidth-constrained mapping ofcores onto NoC architectures, in Design, Automation and Testin Europe, IEEE Computer Society, Paris, France, February16–20, 2004, 896–901.
[5] T. Lei & S. Kumar, A two-step genetic algorithm for mappingtask graphs to a network on chip architecture, in EuromicroSymposium on Digital Systems Design, Belek-Antalya, Turkey,September 1–6, 2003.
[6] S. Kumar, A network on chip architecture and design method-ology, in Proc. ISVLSI ’02, Pittsburgh, PA, April 2002, 105–112.
[7] N. Banerjee, P. Vellanki, & K.S. Chatha, A power and per-formance model for network-on-chip architectures, in Design,Automation and Test in Europe, Paris, France, February 16–20,2004, 1250–1255.
[8] M.R. Garey & D.S. Johnson, Computers and intractability:A guide to the theory of NP-completeness (New York, NY:Freeman & Company, 1979).
[9] L. Benini & G. De Micheli, Networks on chips: A new SoCparadigm, IEEE Computer, January 2002, 70–78.
[10] T.T. Ye, L. Benini, & G.D. Micheli, Analysis of power con-sumption on switch fabrics in network routers, in Proc. DAC’02, June 2002, 524–529.
[11] K. Deb, Multi-objective optimization using evolutionary al-gorithms (West Sussex, England: John Wiley & Sons Ltd,2001).
[12] K. Srinivasan & K.S. Chatha, ISIS: A genetic algorithmbased technique for custom on-chip interconnection networksynthesis, in Proc. 18th International Conf. on VLSI Design(VLSID ’05), Kolkata, India, January 2005.
[13] A.D. Pimentel, S. Polstra, F. Terpstra, A.W. van Halderen,J.E. Coffland, & L.O. Hertzberger, Towards efficient designspace exploration of heterogeneous embedded media systems,in E. Deprettere, J. Teich, & S. Vassiliadis (Eds.), Embeddedprocessor design challenges: systems, architectures, modeling,and simulation, LNCS Vol. 2268 (Springer-Verlag, 2002), pp.7–73.
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DOI:
10.2316/Journal.202.2008.1.202-2506
From Journal
(202) International Journal of Computers and Applications - 2008
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