S.R. Das (Canada, USA), M.H. Assaf, E.M. Petriu, L. Jin, C. Jin, D. Biswas (Canada), and M. Sahinogl
: Built-in self-test (BIST), IP core, module under test (MUT), response compaction unit (RCU), space compression, system-on-a-chip (SoC), test pattern generator (TPG), Verilog VHDL.
To implement fault testing environment for embedded cores based system-on-a-chip (SoC) is a challenging task. This paper proposes digital design verification and test architecture based on relevant hardware and software components. There exist methods to ensure correct SoC functionality in both hardware and software, but one of the most reliable ways to realize this is through the use of design for testability approaches. In particular, applications of built-in self-test (BIST) methodology for testing embedded cores are considered in the paper, with specific implementations being targeted towards ISCAS 85 combinational benchmark circuits.
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